I graduated with a PhD in ECE from NYU Tandon in May 2025. My research focuses on detecting and fixing bugs in Hardware Design Languages using Static Analysis and Generative AI.
Before doing my PhD, I got my Bachelors at NYU Abu Dhabi in Electrical Engineering.
You can read about my work here: Research
Email: ba1283@nyu.edu
Our paper "FLAG: Finding Line Anomalies (in RTL code) with Generative AI" got accepted at Transactions on Design Automation of Electronic Systems.
Our paper "On Hardware Security Bug Code Fixes By Prompting Large Language Models" got accepted at IEEE Transactions on Information Forensics and Security.
Our paper "Verigen: A large language model for verilog code generation" got accepted at ACM Transactions on Design Automation of Electronic Systems.
Our paper "Benchmarking Large Language Models for Automated Verilog RTL Code Generation" got nominated for Best Paper at DATE 2023.
Presented our paper "Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design" at ICCAD 2022.
Our paper "Examining Zero-Shot Vulnerability Repair with Large Language Models" got accepted for IEEE Symposium on Security and Privacy 2023.
Team NYU won Hack@DAC 2022 for the second consecutive year.
Our paper "Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions" won the Distinguished Paper Award at IEEE Symposium on Security and Privacy 2022.
Team NYU won Hack@DAC 2021.
